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Jean Shilpa, V.
- Implementation of Multi-threading on Hybrid Arm Cortex Dual Core A9-fpga Architecture for Energy Efficiency
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1 Department of Electronics & Communication, B. S. Abdur Rahman University, IN
1 Department of Electronics & Communication, B. S. Abdur Rahman University, IN
Source
Indian Journal of Science and Technology, Vol 7, No 12 (2014), Pagination: 2015-2019Abstract
One of the greatest challenges of FPGA is the crave for a platform, which runs a system, handles a software and co-ordinates exchange with peripherals. To explore this advantage on FPGA with energy efficiency, this work aims at developing multithreading on ARM cortex dual core A9 processor present in Zedboard FPGA. To enhance the speed of execution on this processor and to allow concurrency, multithreading is developed using intel thread building blocks(TBB) library which aids in creating task based parallelism on FPGA being the first of its kind. In the first step towards this process, the processor is booted with Ubuntu 12.04 linux operating system making it as a standalone processor. This system is enabled with graphical user interface using xillinux IP library FPGA code kit. To test the efficiency of multihreading on the processing system of Zedboard, an application known as 2D - raytracer is developed using the parallel-for loop scheduling method which aids in running all the iteration loops in the code into chunks and runs each chunk as a separate thread under intel TBB. In this application an image was parallelized by speculating each pixel running in parallel resulting in excellent speedup. The newly implemented multithreading achieves a speedup of 53% compared to sequential execution on the same processor. This method explores the flexibility of parallel processing on FPGA.Keywords
Dual Cortex A9 ARM(advanced Risc Machines) Processor, Field Programmable Gate Array(FPGA), Intel TBB(Thread Building Blocks), Software Development Kit(SDK), Xilinx Platform Studio(XPS), Zedboard(Zynq Evaluation And Development Board)- Reconfigurable Carry Save Adders
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1 Vellore Institute of Technology, IN
1 Vellore Institute of Technology, IN
Source
Programmable Device Circuits and Systems, Vol 3, No 2 (2011), Pagination: 91-95Abstract
Reconfigurable computing is becoming increasingly popular for many applications. In our project, we assimilate and integrate Reconfigurable adder(RA). In this project we present a novel Reconfigurable Adder for summands of different bit width (8, 16, 32 and 64 bits). The whole structure is based on carry save architecture to support multiple summands for increased performance. Our design can be implemented in ASIC as a run time reconfigurable unit. Targeting our architecture for an ASIC platform, the simulation was carried out in Cadence Incisive Unified Simulator. The synthesis done in 180 nm technology using TSMC 18d library in RTL complier. Experimental results show that RA occupies 9% area less compared to the other traditional adder.Keywords
RA: Reconfigurable Adder, ASIC – Application Specific Integrated Circuit, CSa – Carry Save Adders.- Development of Adaptive LMS Filter IP on Zedboard for Hardware-software Co-design
Abstract Views :164 |
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Authors
Affiliations
1 Department of ECE, B.S. Abdur Rahman University, Chennai - 600048, Tamil Nadu, IN
2 Department of ECE, SRM University, IN
1 Department of ECE, B.S. Abdur Rahman University, Chennai - 600048, Tamil Nadu, IN
2 Department of ECE, SRM University, IN